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monolithic 16-bit serial/byte dacport ad660 rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?1993C2008 analog devices, inc. all rights reserved. features complete 16-bit digital-to-analog function on-chip output amplifier on-chip buried zener voltage reference 1 lsb integral linearity 15-bit monotonic over temperature microprocessor compatible serial or byte input double-buffered latches fast (40 ns) write pulse asynchronous clear (to 0 v) function serial output pin facilitates daisy-chaining unipolar or bipolar output low glitch: 15 nv-s low thd + n: 0.009% functional block diagram hbe control logic ser clr ldac ref in 10k? 10k ? 10.05k ? ref out cs db7/ db15 ad660 s out v out agnd span/ bipolar offset dgnd ?v ee +v cc +v ll 10v ref 16-bit latch 16-bit dac 16-bit latch 16 17 18 19 23 24 20 21 22 13 5 1 2 3 4 12 14 15 01813-001 db1/db9/ datadir 11 lbe/ clear select db0/ db8/ sin figure 1. general description the ad660 dacport? is a complete 16-bit monolithic digital- to-analog converter with an on-board voltage reference, double- buffered latches, and an output amplifier. it is manufactured on the analog devices, inc., bimos ii process. this process allows the fabrication of low power cmos logic functions on the same chip as high precision bipolar linear circuitry. the ad660 architecture ensures 15-bit monotonicity over time and temperature. integral and differential nonlinearity is main- tained at 0.003% maximum. the on-chip output amplifier provides a voltage output settling time of 10 s to within ? lsb for a full-scale step. the ad660 has an extremely flexible digital interface. data can be loaded into the ad660 in serial mode or as two 8-bit bytes. this is made possible by two digital input pins that have dual functions. the serial mode input format is pin selectable to be msb or lsb first. the serial output pin allows the user to daisy- chain several ad660 devices by shifting the data through the input latch into the next dac, thus minimizing the number of control lines required to sin, cs and ldac. the byte mode input format is also flexible in that the high byte or low byte data can be loaded first. the double buffered latch structure eliminates data skew errors and provides for simultaneous updating of dacs in a multidac system. the ad660 is available in five grades. an and bn versions are specified from ?40c to +85c and are packaged in a 24-lead 300 mil plastic dip. ar and br versions are also specified from ?40c to +85c and are packaged in a 24-lead soic. the sq version is packaged in a 24-lead 300 mil cerdip package and is also available compliant to mil-std-883. refer to the ad660sq/883b military data sheet for specifications and test conditions. product highlights 1. the ad660 is a complete 16-bit dac, with a voltage reference, double-buffered latches, and an output amplifier on a single chip. 2. the internal buried zener reference is laser trimmed to 10.000 v with a 0.1% maximum error and a temperature drift performance of 15 ppm/c. the reference is available for external applications. 3. the output range of the ad660 is pin programmable and can be set to provide a unipolar output range of 0 v to 10 v or a bipolar output range of ?10 v to +10 v. no external components are required. 4. the ad660 is both dc and ac specified. dc specifications include 1 lsb inl and 1 lsb dnl errors. ac specifica- tions include 0.009% thd + n and 83 db snr. 5. the double-buffered latches on the ad660 eliminate data skew errors and allow simultaneous updating of dacs in multidac applications. 6. the clear function can asynchronously set the output to 0 v regardless of whether the dac is in unipolar or bipolar mode. 7. the output amplifier settles within 10 s to ? lsb for a full-scale step and within 2.5 s for a 1 lsb step over tempera- ture. the output glitch is typically 15 nv-s when a full-scale step is loaded.
ad660 rev. b | page 2 of 20 table of contents features .............................................................................................. 1 ? functional block diagram .............................................................. 1 ? general description ......................................................................... 1 ? product highlights ........................................................................... 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? ac performance characteristics ................................................ 4 ? timing characteristics ................................................................ 5 ? absolute maximum ratings ............................................................ 7 ? esd caution .................................................................................. 7 ? pin configuration and function descriptions ............................. 8 ? terminology ...................................................................................... 9 ? theory of operation ...................................................................... 10 ? analog circuit connections ..................................................... 10 ? unipolar configuration ............................................................. 10 ? bipolar configuration ................................................................ 11 ? internal/external reference use .............................................. 11 ? output settling and glitch ........................................................ 13 ? digital circuit details ................................................................ 14 ? microprocessor interface ............................................................... 15 ? ad660 to mc68hc11 (spi bus) interface ............................. 15 ? ad660 to microwire interface ........................................... 15 ? ad660 to adsp-210x family interface .................................. 15 ? ad660 to z80 interface ............................................................. 16 ? noise ............................................................................................ 16 ? board layout ................................................................................... 17 ? supply decoupling ..................................................................... 17 ? grounding ................................................................................... 17 ? outline dimensions ....................................................................... 18 ? ordering guide .......................................................................... 19 ? revision history 6/08rev. a to rev. b updated format .................................................................. universal updated pin name msb/ lsb to datadir throughout ........... 1 updated pin name uni /bip clear to clear select throughout ....................................................................................... 1 changes to table 1 ............................................................................ 3 changes to endnote 3 in table 1 .................................................... 4 changes to figure 2 .......................................................................... 5 changes to figure 3 and figure 5 ................................................... 6 changes to table 4 ............................................................................. 7 added pin configuration and function descriptions section ... 8 changes to internal/external reference use section ................ 11 changes to figure 12 ...................................................................... 12 changes to figure 13, figure 14, figure 15, and figure 16....... 13 changes to figure 17 and figure 18............................................. 15 changes to figure 19 ...................................................................... 16 updated outline dimensions ....................................................... 18 changes to ordering guide .......................................................... 19
ad660 rev. b | page 3 of 20 specifications t a = 25c, +v cc = 15 v, ?v ee = ?15 v, +v ll = 5 v unless otherwise noted. table 1. parameter ad660an/ar/sq ad660bn/br unit min typ max min typ max resolution 16 16 bits digital inputs (t min to t max ) v ih (logic 1) 2.0 5.5 2.0 5.5 v v il (logic 0) 0 0.8 0 0.8 v i ih (v ih = 5.5 v) ?10 +10 ?10 +10 a i il (v il = 0 v) ?10 +10 ?10 +10 a transfer function characteristics 1 integral nonlinearity bipolar operation ?2 +2 ?1 +1 lsb t min to t max ?4 +4 ?2 +2 lsb unipolar operation ?2 +2 ?1 +1.5 lsb t min to t max ?4 +4 ?2 +2 lsb differential nonlinearity ?2 +2 ?1 +1 lsb t min to t max ?4 +4 ?2 +2 lsb monotonicity over temperature 14 15 bits gain error 2, 3 ?0.1 +0.1 ?0.1 +0.1 % of fsr gain drift (t min to t max ) 25 15 ppm/c dac gain error 4 ?0.05 +0.05 ?0.05 +0.05 % of fsr dac gain drift 4 10 10 ppm/c unipolar offset ?2.5 +2.5 ?2.5 +2.5 mv unipolar offset drift (t min to t max ) 3 3 ppm/c bipolar zero error ?7.5 +7.5 ?7.5 +7.5 mv bipolar zero error drift (t min to t max ) 5 5 ppm/c reference input input resistance 7 10 13 7 10 13 k bipolar offset input resistance 7 10 13 7 10 13 k reference output voltage 9.99 10.00 10.01 9.99 10.00 10.01 v drift 25 15 ppm/c external current 5 2 4 2 4 ma capacitive load 1000 1000 pf short-circuit current 25 25 ma output characteristics output voltage range unipolar configuration 0 +10 0 +10 v bipolar configuration ?10 +10 ?10 +10 v output current 5 5 ma capacitive load 1000 1000 pf short-circuit current 25 25 ma
ad660 rev. b | page 4 of 20 parameter ad660an/ar/sq ad660bn/br unit min typ max min typ max power supplies voltage +v cc 6 +13.5 +16.5 +13.5 +16.5 v ?v ee 6 ?13.5 ?16.5 ?13.5 ?16.5 v +v ll +4.5 +5.5 +4.5 +5.5 v current (no load) i cc +12 +18 +12 +18 ma i ee ?12 ?18 ?12 ?18 ma i ll @ v ih = 5 v, v il = 0 v 0.3 2 0.3 2 ma @ v ih = 2.4 v, v il = 0.4 v 3 7.5 3 7.5 ma power supply sensitivity 1 2 1 2 ppm/% power dissipation (static, no load) 365 625 365 625 mw temperature range specified performance (a, b) ?40 +85 ?40 +85 c specified performance (s) ?55 +125 c 1 for 16-bit resolution, 1 lsb = 0.0015% of fsr. for 15-bit resolution, 1 lsb = 0. 003% of fsr. for 14-bit resolution, 1 lsb = 0. 006% of fsr. fsr stands for full-scale range and is 10 v in a unipolar mode and 20 v in bipolar mode. 2 gain error and gain drift are measured using the internal refe rence. the internal reference is the main contributor to gain dr ift. if lower gain drift is required, the ad660 can be used with a precision external reference such as the ad587, ad586 , or ad688. 3 gain error is measured with fi xed 50 resistors as shown in the theory of ope ration section. eliminating these resistors incr eases the gain error by 0.25% of fsr (unipolar mode) or 0.50% of fsr (bipolar mode). 4 dac gain error and drift are measured with an external voltage reference. they represent the error contributed by the dac alon e, for use with an external reference. 5 external current is defined as the current available in addition to tha t supplied to ref in and span /bipolar offset on the ad6 60. 6 operation on 12 v suppli es is possible using an external reference such as the ad586 and reducing the output range. refer to the internal/external reference use section. ac performance characteristics with the exception of total harmonic distortion + noise (thd + n) and signal-to-noise (snr) ratio, these characteristics are in cluded for design guidance only and are not subject to test. thd + n and snr are 100% tested. t min t a t max , +v cc = 15 v, ?v ee = ?15 v, +v ll = 5 v except where noted. table 2. parameter limit unit test conditions/comments output settling time 13 s max 20 v step, t a = 25c (time to 0.0008% fs 8 s typ 20 v step, t a = 25c with 2 k, 1000 pf load) 10 s typ 20 v step, t min t a t max 6 s typ 10 v step, t a = 25c 8 s typ 10 v step, t min t a t max 2.5 s typ 1 lsb step, t min t a t max total harmonic distortion + noise a, b, s grade 0.009 % max 0 db, 990.5 hz, sample rate = 96 khz, t a = 25c a, b, s grade 0.056 % max ?20 db, 990.5 hz, sample rate = 96 khz, t a = 25c a, b, s grade 5.6 % max ?60 db, 990.5 hz, sample rate = 96 khz, t a = 25c signal-to-noise ratio 83 db min t a = 25c digital-to-analog glitch impulse 15 nv-s typ dac alternately loaded with 0x8000 and 0x7fff digital feedthrough 2 nv-s typ dac alternately loaded with 0x0000 and 0xffff, cs high output noise voltage density (1 khz to 1 mhz) 120 nv/hz typ measured at v out , 20 v span, excludes reference reference noise 125 nv/hz typ measured at ref out
ad660 rev. b | page 5 of 20 timing characteristics +v cc = 15 v, ?v ee = ?15 v, +v ll = 5 v, v high = 2.4 v, v low = 0.4 v. table 3. parameter limit at t a = 25c limit at t a = ?55c to +125c unit byte load (see figure 2) t cs 40 50 ns min t ds 40 50 ns min t dh 0 10 ns min t bes 40 50 ns min t beh 0 10 ns min t lh 80 100 ns min t lw 40 50 ns min serial load (see figure 3) t clk 80 100 ns min t low 30 50 ns min t high 30 50 ns min t ss 0 10 ns min t ds 40 50 ns min t dh 0 10 ns min t sh 0 10 ns min t lh 80 100 ns min t lw 40 50 ns min asynchronous clear to bipolar or unipolar zero (see figure 4) t clr 80 110 ns min t set 80 110 ns min t hold 0 10 ns min serial out (see figure 5) t prop 50 100 ns min t ds 50 80 ns min t ds t dh t lh t lw t beh t bes t cs db0 to db7 hbe or lbe cs ldac 01813-002 figure 2. ad660 byte load timing
ad660 rev. b | page 6 of 20 t lh t lw t clk t low t high db0 valid 1 1 = msb first, 0 = lsb first valid 16 ser ldac db1 (datadir) cs 01813-003 t ss t dh t sh t ds figure 3. ad660 serial load timing c lr lbe 01813-004 t clr t hold t set 1 = bipolar 0, 0 = unipolar 0 figure 4. asynchronous clear to bipolar or unipolar zero db0 s out valid 16 valid 17 valid s out 1 ser db1 ( datadir) cs 01813-005 t ds t prop figure 5. serial out timing
ad660 rev. b | page 7 of 20 absolute maximum ratings table 4. parameter rating +v cc to agnd ?0.3 v to +17.0 v ?v ee to agnd +0.3 v to ?17.0 v +v ll to dgnd ?0.3 v to +7 v agnd to dgnd 1 v digital inputs (pin 5 through pin 23) to dgnd ?1.0 v to +7.0 v ref in to agnd 10.5 v span/bipolar offset to agnd 10.5 v ref out, v out indefinite short to agnd, dgnd, +v cc , ?v ee , and +v ll power dissipation (any package) to +60c 1000 mw derates above +60c 8.7 mw/c storage temperature ?65c to +150c lead temperature jedec industry standard soldering j-std-020 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
ad660 rev. b | page 8 of 20 pin configuration and fu nction descriptions ?v ee 1 +v cc 2 +v ll 3 dgnd 4 ref out 24 ref in 23 span/bipolar offset 22 v out 21 db7/db15 5 agnd 20 db6/db14 6 ldac 19 db5/db13 7 clr 18 db4/db12 8 ser 17 db3/db11 9 hbe 16 db2/db10 10 lbe/clear select 15 db1/db9/datadir 11 cs 14 db0/db8/sin 12 s out 13 ad660 top view (not to scale) 0 1813-006 figure 6. pin configuration table 5. pin function descriptions pin no. mnemonic description 1 ?v ee negative analog supply pin 2 +v cc positive analog supply pin 3 +v ll digital supply pin 4 dgnd digital ground reference pin 5 db7/db15 db7 and db15 byte load data input pin 6 db6/db14 db6 and db14 byte load data input pin 7 db5/db13 db5 and db13 byte load data input pin 8 db4/db12 db4 and db12 byte load data input pin 9 db3/db11 db3 and db11 byte load data input pin 10 db2/db10 db2 and db10 byte load data input pin 11 db1/db9/datadir db1 and db9 byte load data input pin/msb or lsb first data direction se rial input select pin 12 db0/db8/sin db0 and db8 byte load da ta input pin/serial data input pin 13 s out serial data output pin 14 cs chip select pin 15 lbe /clear select low byte enable pin/unipolar or bipolar clear select pin 16 hbe high byte enable pin 17 ser serial input enable pin 18 clr output clear pin 19 ldac load dac pin 20 agnd analog ground reference pin 21 v out voltage output pin 22 span/bipolar offset output span configuration pin 23 ref in external reference voltage input pin 24 ref out internal reference voltage output pin
ad660 rev. b | page 9 of 20 terminology integral nonlinearity integral nonlinearity i s the maximum deviation of the actual, adj usted dac output from the ideal analog output (a straight line drawn from 0 to fs ? 1 lsb) for any bit combination. this is also referred to as relative accuracy. differential nonlinearity differential nonlinearity is the measure of the change in the analog output, normalized to full scale, associated with a 1 lsb change in the digital input code. monotonic behavior requires that the differential linearity error be greater than or equal to ?1 lsb over the temperature range of interest. monotonicity a dac is monotonic if the output either increases or remains constant for increasing digital inputs with the result that the output is always a single-valued function of the input. gain error gain error is a measure of the output error between an ideal dac and the actual device output with all 1s loaded after offset error has been adjusted out. offset error offset error is a combination of the offset errors of the voltage- mode dac and the output amplifier and is measured with all 0s loaded in the dac. bipolar zero error when the ad660 is connected for bipolar output and 10000 is loaded in the dac, the deviation of the analog output from the ideal midscale value of 0 v is called the bipolar zero error. drift drift is the change in a parameter (such as gain, offset, and bipolar zero) over a specified temperature range. the drift temperature coefficient, specified in ppm/c, is calculated by measuring the parameter at t min , 25c, and t max , and dividing the change in the parameter by the corresponding temperature change. total harmonic distortion + noise total harmonic distortion + noise (thd + n) is defined as the ratio of the square root of the sum of the squares of the values of the harmonics and noise to the value of the fundamental input frequency. it is usually expressed in percent (%). thd + n is a measure of the magnitude and distribution of linearity error, differential linearity error, quantization error, and noise. the distribution of these errors may be different, depending upon the amplitude of the output signal. therefore, to be the most useful, thd + n should be specified for both large and small signal amplitudes. signal-to-noise ratio the signal-to-noise ratio is the ratio of the amplitude of the output when a full-scale signal is present to the output with no signal present. the signal-to-noise ratio is measured in decibels (db). digital-to-analog glitch impulse digital-to-analog glitch impulse is the amount of charge injected from the digital inputs to the analog output when the inputs change state. this is measured at half scale when the dac switches around the msb and as many as possible switches change state, that is, from 011111 to 100000. digital feedthrough when the dac is not selected (that is, cs is held high), high frequency logic activity on the digital inputs is capacitively coupled through the device to show up as noise on the v out pin. this noise is digital feedthrough.
ad660 rev. b | page 10 of 20 theory of operation the ad660 uses an array of bipolar current sources with mos current steering switches to develop a current proportional to the applied digital word, ranging from 0 ma to 2 ma. a segmented architecture is used, where the most significant four data bits are thermometer decoded to drive 15 equal current sources. the lesser bits are scaled using a r-2r ladder, then applied together with the segmented sources to the summing node of the output amplifier. the internal span/bipolar offset resistor can be connected to the dac output to provide a 0 v to 10 v span, or it can be connected to the reference input to provide a ?10 v to +10 v span. hbe control logic ser clr ldac ref in 10k ? 10k ? 10.05k ? ref out db0/ db8/ sin db1/db9/ datadir cs db7/ db15 ad660 s out v out agnd span/ bipolar offset dgnd ?v ee +v cc +v ll 10v ref 16-bit latch 16-bit dac 16-bit latch 16 17 18 19 23 24 20 21 22 13 5 1 2 3 4 11 12 14 15 01813-007 lbe/ clear select figure 7. functional block diagram analog circuit connections internal scaling resistors provided in the ad660 can be connected to produce a unipolar output range of 0 v to 10 v or a bipolar output range of ?10 v to +10 v. gain and offset drift are mini- mized in the ad660 because of the thermal tracking of the scaling resistors with other device components. unipolar configuration the configuration shown in figure 8 provides a unipolar 0 v to 10 v output range. in this mode, 50 resistors are tied between the span/bipolar offset terminal (pin 22) and v out (pin 21), and between ref out (pin 24) and ref in (pin 23). it is possible to use the ad660 without any external components by tying pin 24 directly to pin 23 and pin 22 directly to pin 21. eliminating these resistors increases the gain error by 0.25% of fsr. hbe control logic ser clr ldac ref in ref out ad660 s out v out agnd output r2 50 ? r1 50? span/ bipolar offset dgnd ?v ee +v cc +v ll 10v ref 16-bit latch 16-bit dac 16 17 18 19 23 24 20 21 22 13 1 2 3 4 15 01813-008 10k? 10k? 10.05k ? db1/db9/ datadir 11 lbe/ clear select db0/ db8/ sin cs db7/ db15 5 12 14 16-bit latch figure 8. 0 v to 10 v unipolar voltage output if it is desired to adjust the gain and offset errors to zero, this can be accomplished using the circuit shown in figure 9. the adjustment procedure is as follows: 1. zero adjust. turn all bits off and adjust the zero trimmer, r4, until the output reads 0.000000 v (1 lsb = 153 v). 2. gain adjust. turn all bits on and adjust the gain trimmer, r1, until the output is 9.999847 v. (full scale is adjusted to 1 lsb less than the nominal full scale of 10.000000 v.) hbe control logic ser clr ldac ref in ref out ad660 s out v out agnd output r2 50 ? r3 16k r4 10k r1 100 ? span/ bipolar offset dgnd ?v ee +v cc ?v ee +v cc +v ll 10v ref 16-bit latch 16-bit dac 16 17 18 19 23 24 20 21 22 13 1 2 3 4 15 01813-009 10k ? 10k? 10.05k ? db1/db9/ datadir 11 lbe/ clear select db0/ db8/ sin cs db7/ db15 5 12 14 16-bit latch figure 9. 0 v to 10 v unipolar voltage output with gain and offset adjustment
ad660 rev. b | page 11 of 20 bipolar configuration the circuit shown in figure 10 provides a bipolar output voltage from ?10.000000 v to +9.999694 v with positive full scale occur- ring with all bits on. as in the unipolar mode, resistor r1 and resistor r2 can be eliminated altogether to provide ad660 bipolar operation without any external components. eliminating these resistors increases the gain error by 0.50% of fsr in bipolar mode. hbe control logic ser clr ldac ref in r1 50? r2 50? ref out ad660 s out v out agnd span/ bipolar offset dgnd ?v ee +v cc +v ll 10v ref 16-bit latch 16-bit dac 16 17 18 19 23 24 20 21 22 13 1 2 3 4 15 01813-010 output 10k ? 10k? 10.05k ? db1/db9/ datadir 11 lbe/ clear select db0/ db8/ sin cs db7/ db15 5 12 14 16-bit latch figure 10. 10 v bipolar voltage output gain offset and bipolar zero errors can be adjusted to zero using the circuit shown in figure 11 as follows: 1. offset adjust. turn off all bits. adjust the trimmer, r2, to give 10.000000 v output. 2. gain adjust. turn all bits on and adjust r1 to give a reading of 9.999694 v. 3. bipolar zero adjust (optional). in applications where an accurate zero output is required, set the msb on, all other bits off, and readjust r2 for 0 v output. hbe control logic ser clr ldac ref in r1 50? ref out ad660 s out v out agnd span/ bipolar offset dgnd ?v ee +v cc +v ll 10v ref 16-bit latch 16-bit dac 16 17 18 19 23 24 20 21 22 13 1 2 3 4 15 01813-011 output r2 100? 10k ? 10k? 10.05k ? db1/db9/ datadir 11 lbe/ clear select db0/ db8/ sin cs db7/ db15 5 12 14 16-bit latch figure 11. 10 v bipolar voltage output with gain and offset adjustment note that using external resistors introduces a small temperature drift component beyond that inherent in the ad660. the inter- nal resistors are trimmed to ratio-match and temperature-track other resistors on-chip, even though their absolute tolerances are 20% and absolute temperature coefficients are approximately ?50 ppm/c. in the case that external resistors are used, the temperature coefficient mismatch between internal and external resistors, multiplied by the sensitivity of the circuit to variations in the external resistor value, is the resultant additional tempera- ture drift. internal/external reference use the ad660 has an internal low noise buried zener diode reference that is trimmed for absolute accuracy and temperature coefficient. this reference is buffered and optimized for use in a high speed dac and gives long-term stability equal or superior to the best discrete zener diode references. the performance of the ad660 is specified with the internal reference driving the dac and with the dac alone (for use with a precision external reference). the internal reference has sufficient buffering to drive external circuitry in addition to the reference currents required for the dac (typically 1 ma to ref in and 1 ma to span/bipolar offset). a minimum of 2 ma is available for driving external loads. the ad660 reference output should be buffered with an external op amp if it is required to supply more than 4 ma total current. the reference is tested and guaranteed to 0.2% maximum error.
ad660 rev. b | page 12 of 20 it is also possible to use external references other than 10 v with slightly degraded linearity specifications. the recommended range of reference voltages is 5 v to 10.24 v, which allows 5 v, 8.192 v, and 10.24 v ranges to be used. for example, by using the ad586 5 v reference, outputs of 0 v to 5 v unipolar or 5 v bipolar can be realized. using the ad586 voltage reference makes it possible to operate the ad660 with 12 v supplies with 10% tolerances. figure 12 shows the ad660 using the ad586 precision 5 v reference in the bipolar configuration. the highest grade ad586mn is specified with a drift of 2 ppm/c, which is a 7.5 improvement over the ad660 internal reference. this circuit includes two optional potentiometers and one optional resistor that can be used to adjust the gain, offset, and bipolar zero errors in a manner similar to that described in the bipolar configuration section. use ?5.000000 v and +4.999847, as the output values. the ad660 can also be used with the ad587 10 v reference, using the same configuration shown in figure 12 to produce a 10 v output. the highest grade ad587uq is specified at 5 ppm/c, which is a 3 improvement over the ad660 internal reference. figure 13 shows the ad660 using the ad688 precision 10 v reference, in the unipolar configuration. the highest grade ad688bq is specified with a temperature coefficient of 1.5 ppm/c. the 10 v output is also ideal for providing precise biasing for the offset trim resistor, r4. hbe control logic ser clr ldac ref in gnd trim v out v in r1 50? r2 10k? r2 50? ref out ad660 ad586 s out v out agnd span/ bipolar offset dgnd ?v ee +v cc +v ll 10v ref 16-bit latch 16-bit dac 16 17 18 19 23 24 20 21 22 13 1 2 3 4 15 01813-012 output 6 5 4 2 10k ? 10k? 10.05k ? db1/db9/ datadir 11 lbe/ clear select db0/ db8/ sin cs db7/ db15 5 12 14 16-bit latch figure 12. using the ad660 with the ad586 5 v reference
ad660 rev. b | page 13 of 20 hbe control logic ser clr ldac ref in r1 50 ? r6 r5 r2 r3 r s r1 r4 r2 50 ? ref out ad660 ad688 s out v out agnd span/ bipolar offset dgnd ?v ee +v cc +v ll 10v ref 16-bit latch 16-bit dac 16 17 18 19 23 24 20 21 22 13 1 2 3 4 15 01813-013 output 0v to 10v r2 100? r3 10k ? r4 10k? ?v s +v s 14 1 15 2 16 13 11 12 8 10 9 5 a3 a2 a4 a1 4 6 7 3 10k? 10k? 10.05k ? db1/db9/ datadir 11 lbe/ clear select db0/ db8/ sin cs db7/ db15 5 12 14 16-bit latch figure 13. using the ad660 with the ad688 high precision 10 v reference output settling and glitch the ad660 output buffer amplifier typically settles to within 0.0008% fs (1/2 lsb) of its final value in 8 s for a full-scale step. figure 14 and figure 15 show settling for a full-scale and an lsb step, respectively, with a 2 k, 1000 pf load applied. the guaranteed maximum settling time at 25c for a full-scale step is 13 s with this load. the typical settling time for a 1 lsb step is 2.5 s. the digital-to-analog glitch impulse is specified as 15 nv-s typical. figure 16 shows the typical glitch impulse characteristic at the 011111 to 100000 code transition when loading the second rank register from the first rank register. +10 0 600 400 200 0 ?200 ?400 ?600 ?10 01 02 0 01813-014 output voltage (v) output voltage (v) time (s) figure 14. ?10 v to +10 v full-scale step settling 01 2345 01813-015 output voltage (v) time (s) 600 400 200 0 ?200 ?400 ?600 figure 15. lsb step settling +10 0 ?10 01813-016 output voltage (mv) time (s) 01 2345 figure 16. output characteristics
ad660 rev. b | page 14 of 20 digital circuit details the ad660 has several dual-use pins that allow flexible opera- tion while maintaining the lowest possible pin count and consequently the smallest package size. the user should, therefore, pay careful attention to the following information when applying the ad660. data can be loaded into the ad660 in serial or byte mode, described as follows. serial mode operation is enabled by bringing ser (pin 17) low. this changes the function of db0 (pin 12) to that of the serial input pin, sin. it also changes the function of db1 (pin 11) to a control input that tells the ad660 whether the serial data is going to be loaded msb or lsb first. in serial mode, hbe and lbe are effectively disabled except for the dual function of lbe , which is to control whether the asynchronous clear function goes to unipolar or bipolar zero. (a low on lbe , when clr is strobed, sends the dac output to unipolar zero, a high to bipolar zero.) the ad660 does not recognize the status of hbe when in serial mode. data is clocked into the input register on the rising edge of cs , as shown in figure 3. the data then resides in the first rank latch and can be loaded into the dac latch by taking ldac high. this causes the dac to change to the appropriate output value. it should be noted that the clr function clears the dac latch but does not clear the first rank latch. therefore, the data that was previously residing in the first rank latch can be reloaded simply by bringing ldac high after the event that necessitated clr to be strobed has ended. alternatively, new data can be loaded into the first rank latch if desired. the serial out pin (s out ) can be used to daisy-chain several dacs together in multidac applications to minimize the number of isolators being used to cross an intrinsic safety barrier. the first rank latch acts like a 16-bit shift register, and repeated strobing of cs shifts the data out through s out and into the next dac. each dac in the chain requires its own ldac signal unless all of the dacs are to be updated simultaneously. byte mode operation is enabled simply by keeping ser high, which configures db0 to db7 as data inputs. in this mode, hbe and lbe are used to identify the data as either the high byte or the low byte of the 16-bit input word. (the user can load the data, in any order, into the first rank latch.) as in the serial mode case, the status of lbe , when clr is strobed, determines whether the ad660 clears to unipolar or bipolar zero. therefore, when in byte mode, the user must take care to set lbe to the desired status before strobing clr . (in serial mode the user can simply hardware lbe to the desired state.) note that cs is edge triggered. hbe , lbe , and ldac are level triggered.
ad660 rev. b | page 15 of 20 microprocessor interface ad660 to mc68hc11 (spi bus) interface the ad660 interface to the motorola spi (serial peripheral interface) is shown in figure 17. the mosi, sck, and ss pins of the 68hc11 are respectively connected to the db0/db8/sin, cs , and ldac pins of the ad660. the ser pin of the ad660 is tied low causing the first rank latch to be transparent. the majority of the interfacing issues are taken care of in the software initialization. a typical routine such as the one shown in the software initialization example begins by initializing the state of the various spi data and control registers. the most significant data byte (msby) is then retrieved from memory and processed by the sendat subroutine. the ss pin is driven low by indexing into the portd data register and clearing bit 5. this causes the 2nd rank latch of the ad660 to become transparent. the msby is then set to the spi data register where it is automatically transferred to the ad660. the hc11 generates the requisite eight clock pulses with data valid on the rising edges. after the most significant byte is transmitted, the least significant byte (lsby) is loaded from memory and transmitted in a similar fashion. to complete the transfer, the ldac pin is driven high, latching the complete 16-bit word into the ad660. software initialization example init ldaa #$2f ; ss = i; sck = 0; mosi = i staa portd ;send to spi outputs ldaa #$38 ; ss , sck,mosi = outputs staa ddrd ;send data direction info ldaa #$50 ;dabl intrpts,spi is master & on staa spcr ;cpol = 0, cpha = 0,1mhz baud rate nextpt ldaa msby ;load accum with upper 8 bits bsr sendat ;jump to dac output routine jmp nextpt ;infinite loop sendat ldy #$1000 ;point at on-chip registers bclr $08,y,$20 ;drive ss (ldac) low staa spdr ;send ms-byte to spi data reg wait1 ldaa spsr ;check status of spie bpl wait1 ;poll for end of x- mission ldaa lsby ;get low 8 bits from memory staa spdr ;send ls-byte to spi data reg wait2 ldaa spsr ;check status of spie bpl wait2 ;poll for end of x- mission bset $08,y,$20 ;driv ss high to latch data rts db0/db8/sin cs ldac mdsi sck ss ad660 68hc11 ser 01813-017 figure 17. ad660 to 68hc11 (spi) interface ad660 to microwire interface the flexible serial interface of the ad660 is also compatible with the national semiconductor microwire? interface. the microwire interface is used on microcontrollers, such as the cop400 and cop800 series of processors. a generic interface to the microwire interface is shown in figure 18. the g1, sk, and so pins of the microwire interface are respec- tively connected to the ldac, cs and db0/db8/sin pins of the ad660. db0/db8/sin cs ldac so sk g1 ad660 microwire? ser 01813-018 figure 18. ad660 to microwire interface ad660 to adsp-210x family interface the serial mode of the ad660 minimizes the number of control and data lines required to interface to digital signal processors (dsps) such as the adsp-210x family. the application in figure 19 shows the interface between an adsp-210x and the ad660. both the tfs pin and the dt pins of the adsp-210x should be connected to the ser and db0 pins of the ad660, respectively. an inverter is required between the sclk output and the cs input of the ad660 to ensure that data transmitted to the db0 pin is valid on the rising edge of cs . the serial port (sport) of the dsp should be configured for alternate framing mode so that tfs complies with the word length framing requirement of ser . note that the invtfs bit in the sport control register should be set to invert the tfs signal so that ser is the correct polarity. the ldac signal, which must meet the minimum hold specification of t high , is easily generated by delaying the rising edge of ser with a 74hc74 flip-flop. the cs signal clocks the flip-flop, resulting in a delay of approximately one cs clock cycle.
ad660 rev. b | page 16 of 20 in applications such as waveform generation, accurate timing of the output samples is important to avoid noise that is induced by jitter on the ldac signal. in this example, the adsp-210x is set up to use the internal timer to interrupt the processor at the precise and desired sample rate. when the timer interrupt occurs, the 16-bit data word of the processor is written to the transmit register (txn). this causes the dsp to automatically generate the tfs signal and begin transmission of the data. db0/db8/sin cs ldac sclk dt tfs ad660 adsp-210x 74hc04 74hc74 ser 01813-019 d q figure 19. ad660 to adsp-210x interface ad660 to z80 interface figure 20 shows a zilog z80 8-bit microprocessor connected to the ad660 using the byte mode interface. the double-buffered capability of the ad660 allows the microprocessor to indepen- dently write to the low and high byte registers, and update the dac output. processor speeds up to 6 mhz on the z80 require no extra wait states to interface with the ad660 when using a 74als138 as the address decoder. the address decoder analyzes the input-output address produced by the processor to select the function to be performed by the ad660, qualified by the coincidence of the input/output request ( iorq ) and write ( wr ) pins. the least significant address bit (a0) determines if the low or high byte register of the ad660 is active. more significant address bits select between input register loading, dac output update, and unipolar or bipolar clear. a typical z80 software routine begins by writing the low byte of the desired 16-bit dac data to address 0, followed by the high byte to address 1. the dac output is then updated by activating ldac with a write to address 2 (or address 3). a clear to unipolar zero occurs on a write to address 4, and a clear to bipolar zero is performed by a write to address 5. the actual data written to address 2 through address 5 is irrelevant. the decoder can easily be expanded to control as many ad660 devices as required. db0 to db7 +v ll clr ldac ad660 z80 cs y2 a1 to a15 a0 to a15 d0 to d7 y1 e2 e1 iorq wr y0 a0 ser hbe dgnd 01813-020 address decode lbe figure 20. connections for 8-bit bus interface noise in high resolution systems, noise is often the limiting factor. a 16-bit dac with a 10 v span has an lsb size of 153 v (?96 db). therefore, the noise floor must remain below this level in the frequency range of interest. the noise spectral density of the ad660 is shown in figure 21 and figure 22. figure 21 shows the dac output noise voltage spectral density for a 20 v span excluding the reference. this figure shows the 1/f corner frequency at 100 hz and the wideband noise to be below 120 nv/hz. figure 22 shows the reference noise voltage spectral density and shows the reference wideband noise to be below 125 nv/hz. 1k 100 10 1 1 10 100 1k 10k 100k 1m 10m noise voltage (nv/ hz) frequency (hz) 01813-021 figure 21. dac output noise voltage spectral density 1k 100 10 1 1 10 100 1k 10k 100k 1m 10m noise voltage (nv/ hz) frequency (hz) 01813-022 figure 22. reference noise voltage spectral density
ad660 rev. b | page 17 of 20 board layout designing with high resolution data converters requires careful attention to board layout. trace impedance is the first issue. a 306 a current through a 0.5 trace develops a voltage drop of 153 v, which is 1 lsb at the 16-bit level for a 10 v full-scale span. in addition to ground drops, inductive and capacitive coupling need to be considered, especially when high accuracy analog signals share the same board with digital signals. finally, power supplies need to be decoupled to filter out ac noise. analog and digital signals should not share a common path. each signal should have an appropriate analog or digital return routed close to it. using this approach, signal loops enclose a small area, minimizing the inductive coupling of noise. wide pc tracks, large gauge wire, and ground planes are highly recommended to provide low impedance signal paths. separate analog and digital ground planes should also be used, with a single interconnection point to minimize ground loops. analog signals should be routed as far as possible from digital signals and should cross them at right angles. one feature that the ad660 incorporates to help the user layout is that the analog pins (+v cc , ?v ee , ref out, ref in, span/ bipolar offset, v out and agnd) are adjacent to help isolate analog signals from digital signals. supply decoupling the ad660 power supplies should be well filtered, well regulated, and free from high frequency noise. switching power supplies are not recommended due to their tendency to generate spikes, which can induce noise in the analog system. decoupling capacitors should be used in very close layout proximity between all power supply pins and ground. a 10 f tantalum capacitor in parallel with a 0.1 f ceramic capacitor provides adequate decoupling. v cc and v ee should be bypassed to analog ground, while v ll should be decoupled to digital ground. an effort should be made to minimize the trace length between the capacitor leads and the respective converter power supply and common pins. the circuit layout should attempt to locate the ad660, associated analog circuitry, and interconnections as far as possible from logic circuitry. a solid analog ground plane around the ad660 will isolate large switching ground currents. for these reasons, the use of wire wrap circuit construction is not recommended; careful printed circuit construction is preferred. grounding the ad660 has two ground pins, designated analog ground (agnd) and digital ground (dgnd.) the analog ground pin is the high quality ground reference point for the device. any external loads on the output of the ad660 should be returned to analog ground. if an external reference is used, this should also be returned to the analog ground. if a single ad660 is used with separate analog and digital ground planes, connect the analog ground plane to agnd and the digital ground plane to dgnd keeping lead lengths as short as possible. then connect agnd and dgnd together at the ad660. if multiple ad660 devices are used or the ad660 shares analog supplies with other components, connect the analog and digital returns together once at the power supplies rather than at each chip. this single interconnection of grounds prevents large ground loops and consequently prevents digital currents from flowing through the analog ground.
ad660 rev. b | page 18 of 20 outline dimensions controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design. corner leads may be configured as whole or half leads. compliant to jedec standards ms-001 071006-a 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) 0.150 (3.81) 0.130 (3.30) 0.115 (2.92) 0.070 (1.78) 0.060 (1.52) 0.045 (1.14) 24 1 12 13 0.100 (2.54) bsc 1.280 (32.51) 1.250 (31.75) 1.230 (31.24) 0.210 (5.33) max seating plane 0.015 (0.38) min 0.005 (0.13) min 0.280 (7.11) 0.250 (6.35) 0.240 (6.10) 0.060 (1.52) max 0.430 (10.92) max 0.014 (0.36) 0.010 (0.25) 0.008 (0.20) 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) 0.015 (0.38) gauge plane 0.195 (4.95) 0.130 (3.30) 0.115 (2.92) figure 23. 24-lead plastic dual in-line package [pdip] narrow body (n-24-1) dimensions shown in inches and (millimeters) controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design. 24 11 2 13 0.310 (7.87) 0.220 (5.59) 0.005 (0.13) min 0.098 (2.49) max 15 0 0.320 (8.13) 0.290 (7.37) 0.015 (0.38) 0.008 (0.20) seating plane 0.200 (5.08) max 1.280 (32.51) max 0.150 (3.81) min 0.200 (5.08) 0.125 (3.18) 0.023 (0.58) 0.014 (0.36) 0.100 (2.54) bsc 0.070 (1.78) 0.030 (0.76) 0.060 (1.52) 0.015 (0.38) pin 1 figure 24. 24-lead ceramic dual in-line package [cerdip] (q-24) dimensions shown in inches and (millimeters)
ad660 rev. b | page 19 of 20 compliant to jedec standards ms-013-ad controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design. 15.60 (0.6142) 15.20 (0.5984) 0.30 (0.0118) 0.10 (0.0039) 2.65 (0.1043) 2.35 (0.0925) 10.65 (0.4193) 10.00 (0.3937) 7.60 (0.2992) 7.40 (0.2913) 0 . 7 5 ( 0 . 0 2 9 5 ) 0 . 2 5 ( 0 . 0 0 9 8 ) 45 1.27 (0.0500) 0.40 (0.0157) coplanarity 0.10 0.33 (0.0130) 0.20 (0.0079) 0.51 (0.0201) 0.31 (0.0122) seating plane 8 0 24 13 12 1 1.27 (0.0500) bsc 060706-a figure 25. 24-lead standard small outline package [soic_w] wide body (rw-24) dimensions shown in millimeters and (inches) ordering guide model temperature range gain tc max ppm/ c package description package option ad660an ?40c to +85c 25 24-lead pdip n-24-1 ad660anz 1 ?40c to +85c 25 24-lead pdip n-24-1 ad660ar ?40c to +85c 25 24-lead soic_w rw-24 ad660ar-reel ?40c to +85c 25 24-lead soic_w rw-24 ad660arz 1 ?40c to +85c 25 24-lead soic_w rw-24 ad660arz-reel 1 ?40c to +85c 25 24-lead soic_w rw-24 ad660bn ?40c to +85c 15 24-lead pdip n-24-1 ad660bnz 1 ?40c to +85c 15 24-lead pdip n-24-1 ad660br ?40c to +85c 15 24-lead soic_w rw-24 ad660br-reel ?40c to +85c 15 24-lead soic_w rw-24 ad660brz 1 ?40c to +85c 15 24-lead soic_w rw-24 AD660BRZ-REEL 1 ?40c to +85c 15 24-lead soic_w rw-24 ad660sq ?55c to +125c 25 24-lead cerdip q-24 ad660sq/883b 2 ?55c to +125c 1 z = rohs compliant part. 2 for further details, refer to the ad660sq/883b milit ary data sheet.
ad660 rev. b | page 20 of 20 notes ?1993C2008 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d01813-0-6/08(b)

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